From a40fbb874e226bf5368c8e5435fc322aa5d41a70 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 18:40:15 +0200
Subject: Rename verilog series include

---
 _includes/series_verilog.md                               | 12 ++++++++++++
 _includes/verilog.md                                      | 12 ------------
 _posts/2025-12-26-fpga-dev-board.md                       |  2 +-
 _posts/2026-01-06-getting-started-with-verilog.md         |  2 +-
 _posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md |  2 +-
 5 files changed, 15 insertions(+), 15 deletions(-)
 create mode 100644 _includes/series_verilog.md
 delete mode 100644 _includes/verilog.md

diff --git a/_includes/series_verilog.md b/_includes/series_verilog.md
new file mode 100644
index 0000000..fbc1659
--- /dev/null
+++ b/_includes/series_verilog.md
@@ -0,0 +1,12 @@
+
+---
+{: .spaced.top }
+
+## Verilog series
+
+0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
+1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
+2. [How does a CPU actually work?]({% post_url 2026-03-22-verilog-how-does-a-cpu-actually-work %})
+
+---
+{: .spaced.bottom }
diff --git a/_includes/verilog.md b/_includes/verilog.md
deleted file mode 100644
index fbc1659..0000000
--- a/_includes/verilog.md
+++ /dev/null
@@ -1,12 +0,0 @@
-
----
-{: .spaced.top }
-
-## Verilog series
-
-0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
-1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
-2. [How does a CPU actually work?]({% post_url 2026-03-22-verilog-how-does-a-cpu-actually-work %})
-
----
-{: .spaced.bottom }
diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 49380c4..7bb0280 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -7,7 +7,7 @@ date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index e3b3e14..33672b4 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,7 +7,7 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
diff --git a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
index 63d8951..539271e 100644
--- a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
+++ b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
@@ -7,7 +7,7 @@ date: 2026-03-22 16:55 +0100
 description: How to write a CPU in Verilog
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 A.k.a. "What's a fetch-decode-execute" cycle?
 
-- 
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