From f704e93efac8193447543e518068c3d0ad1c3689 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 15 Mar 2026 13:52:55 +0100
Subject: Include TOC for Verilog series

---
 _config.yml                                       |  2 +-
 _includes/verilog.md                              | 12 ++++++++++++
 _posts/2025-12-26-fpga-dev-board.md               |  2 ++
 _posts/2026-01-06-getting-started-with-verilog.md |  2 ++
 assets/main.scss                                  |  7 +++++++
 5 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 _includes/verilog.md

diff --git a/_config.yml b/_config.yml
index 6f24434..0d0af53 100644
--- a/_config.yml
+++ b/_config.yml
@@ -71,7 +71,7 @@ autopages:
   collections:
     enabled: false
 
-cssversion: "2025110301"
+cssversion: "2026031502"
 
 feed:
   posts_limit: 20
diff --git a/_includes/verilog.md b/_includes/verilog.md
new file mode 100644
index 0000000..d89bbb0
--- /dev/null
+++ b/_includes/verilog.md
@@ -0,0 +1,12 @@
+
+---
+{: .spaced.top }
+
+## Verilog series
+
+0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
+1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
+2. TODO
+
+---
+{: .spaced.bottom }
diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 17c871e..49380c4 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -7,6 +7,8 @@ date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
 ---
 
+{% include verilog.md %}
+
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
 urge to "find the perfect solution", in this case, the perfect
diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 994699b..e3b3e14 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,6 +7,8 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
+{% include verilog.md %}
+
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
 start with Verilog. The book contained a few exercises which I tried to
diff --git a/assets/main.scss b/assets/main.scss
index b5f2fa5..6a6e664 100644
--- a/assets/main.scss
+++ b/assets/main.scss
@@ -88,6 +88,13 @@ hr.postsep {
   display: none;
 }
 
+hr.spaced.bottom {
+  margin-bottom: 1em;
+}
+hr.spaced.top {
+  margin-bottom: 0.5em;
+}
+
 /*
 PUSH CSS VERSION!
 */
-- 
cgit v1.2.3