From a40fbb874e226bf5368c8e5435fc322aa5d41a70 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 18:40:15 +0200
Subject: Rename verilog series include

---
 _includes/series_verilog.md | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 _includes/series_verilog.md

(limited to '_includes/series_verilog.md')

diff --git a/_includes/series_verilog.md b/_includes/series_verilog.md
new file mode 100644
index 0000000..fbc1659
--- /dev/null
+++ b/_includes/series_verilog.md
@@ -0,0 +1,12 @@
+
+---
+{: .spaced.top }
+
+## Verilog series
+
+0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
+1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
+2. [How does a CPU actually work?]({% post_url 2026-03-22-verilog-how-does-a-cpu-actually-work %})
+
+---
+{: .spaced.bottom }
-- 
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