From bca915d2f3e399528b629a4502a3804e5b22cbb0 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 22 Mar 2026 16:57:14 +0100
Subject: Add Verilog-CPU

---
 _includes/verilog.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to '_includes/verilog.md')

diff --git a/_includes/verilog.md b/_includes/verilog.md
index d89bbb0..fbc1659 100644
--- a/_includes/verilog.md
+++ b/_includes/verilog.md
@@ -6,7 +6,7 @@
 
 0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
 1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
-2. TODO
+2. [How does a CPU actually work?]({% post_url 2026-03-22-verilog-how-does-a-cpu-actually-work %})
 
 ---
 {: .spaced.bottom }
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