From a40fbb874e226bf5368c8e5435fc322aa5d41a70 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 18:40:15 +0200
Subject: Rename verilog series include

---
 _posts/2025-12-26-fpga-dev-board.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to '_posts/2025-12-26-fpga-dev-board.md')

diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 49380c4..7bb0280 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -7,7 +7,7 @@ date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
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