From f704e93efac8193447543e518068c3d0ad1c3689 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 15 Mar 2026 13:52:55 +0100
Subject: Include TOC for Verilog series

---
 _posts/2025-12-26-fpga-dev-board.md | 2 ++
 1 file changed, 2 insertions(+)

(limited to '_posts/2025-12-26-fpga-dev-board.md')

diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 17c871e..49380c4 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -7,6 +7,8 @@ date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
 ---
 
+{% include verilog.md %}
+
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
 urge to "find the perfect solution", in this case, the perfect
-- 
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