From 522f98fc205d112897360fa90bbbef268aa66f48 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 19:08:38 +0200
Subject: Use auto-series

---
 _posts/2026-01-06-getting-started-with-verilog.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to '_posts/2026-01-06-getting-started-with-verilog.md')

diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 33672b4..c0044c0 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -5,9 +5,10 @@ date: 2026-01-06 15:52 +0100
 categories: tech
 lang: en
 description: "First experiments with Verilog, mostly simuluated."
+series: Verilog
 ---
 
-{% include series_verilog.md %}
+{% include series.md %}
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
-- 
cgit v1.2.3