From 8e478c5fbc4b97f9538cead8ae9667a45c5c8ede Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Fri, 27 Feb 2026 18:00:07 +0100
Subject: Add description tags

---
 _posts/2026-01-06-getting-started-with-verilog.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to '_posts/2026-01-06-getting-started-with-verilog.md')

diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 8eaf5f4..994699b 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -4,6 +4,7 @@ title: Getting started with Verilog
 date: 2026-01-06 15:52 +0100
 categories: tech
 lang: en
+description: "First experiments with Verilog, mostly simuluated."
 ---
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
@@ -45,4 +46,3 @@ syntax first, because I don't like the syntax nand2tetris introduces. That's not
 "proper assembler" for me. One of the special things of the architecture is that
 you can have multiple "destinations" for an operation, though - or none at all.
 To my shame, I used an LLM to get inspiration how the language could look like. 
-
-- 
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