From a40fbb874e226bf5368c8e5435fc322aa5d41a70 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 18:40:15 +0200
Subject: Rename verilog series include

---
 _posts/2026-01-06-getting-started-with-verilog.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to '_posts/2026-01-06-getting-started-with-verilog.md')

diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index e3b3e14..33672b4 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,7 +7,7 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
-- 
cgit v1.2.3