From f704e93efac8193447543e518068c3d0ad1c3689 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 15 Mar 2026 13:52:55 +0100
Subject: Include TOC for Verilog series

---
 _posts/2026-01-06-getting-started-with-verilog.md | 2 ++
 1 file changed, 2 insertions(+)

(limited to '_posts/2026-01-06-getting-started-with-verilog.md')

diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 994699b..e3b3e14 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,6 +7,8 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
+{% include verilog.md %}
+
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
 start with Verilog. The book contained a few exercises which I tried to
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