From 522f98fc205d112897360fa90bbbef268aa66f48 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 19:08:38 +0200
Subject: Use auto-series

---
 _posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to '_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md')

diff --git a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
index 539271e..0ebfafc 100644
--- a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
+++ b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
@@ -5,9 +5,10 @@ lang: en
 categories: tech
 date: 2026-03-22 16:55 +0100
 description: How to write a CPU in Verilog
+series: Verilog
 ---
 
-{% include series_verilog.md %}
+{% include series.md %}
 
 A.k.a. "What's a fetch-decode-execute" cycle?
 
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