From a40fbb874e226bf5368c8e5435fc322aa5d41a70 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 18:40:15 +0200
Subject: Rename verilog series include

---
 _posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to '_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md')

diff --git a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
index 63d8951..539271e 100644
--- a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
+++ b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
@@ -7,7 +7,7 @@ date: 2026-03-22 16:55 +0100
 description: How to write a CPU in Verilog
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 A.k.a. "What's a fetch-decode-execute" cycle?
 
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