From 522f98fc205d112897360fa90bbbef268aa66f48 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 14 Jun 2026 19:08:38 +0200
Subject: Use auto-series

---
 _posts/2025-12-26-fpga-dev-board.md                       | 3 ++-
 _posts/2026-01-06-getting-started-with-verilog.md         | 3 ++-
 _posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

(limited to '_posts')

diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 7bb0280..4522928 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -5,9 +5,10 @@ lang: en
 categories: tech
 date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
+series: Verilog
 ---
 
-{% include series_verilog.md %}
+{% include series.md %}
 
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 33672b4..c0044c0 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -5,9 +5,10 @@ date: 2026-01-06 15:52 +0100
 categories: tech
 lang: en
 description: "First experiments with Verilog, mostly simuluated."
+series: Verilog
 ---
 
-{% include series_verilog.md %}
+{% include series.md %}
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
diff --git a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
index 539271e..0ebfafc 100644
--- a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
+++ b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
@@ -5,9 +5,10 @@ lang: en
 categories: tech
 date: 2026-03-22 16:55 +0100
 description: How to write a CPU in Verilog
+series: Verilog
 ---
 
-{% include series_verilog.md %}
+{% include series.md %}
 
 A.k.a. "What's a fetch-decode-execute" cycle?
 
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