From f704e93efac8193447543e518068c3d0ad1c3689 Mon Sep 17 00:00:00 2001
From: uvok cheetah
Date: Sun, 15 Mar 2026 13:52:55 +0100
Subject: Include TOC for Verilog series

---
 assets/main.scss | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'assets/main.scss')

diff --git a/assets/main.scss b/assets/main.scss
index b5f2fa5..6a6e664 100644
--- a/assets/main.scss
+++ b/assets/main.scss
@@ -88,6 +88,13 @@ hr.postsep {
   display: none;
 }
 
+hr.spaced.bottom {
+  margin-bottom: 1em;
+}
+hr.spaced.top {
+  margin-bottom: 0.5em;
+}
+
 /*
 PUSH CSS VERSION!
 */
-- 
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