fpga-exper/Makefile, branch mainFPGA experimentshttps://git.uvok.de/fpga-exper/atom?h=main2026-01-09T14:18:23Zmove stuff around2026-01-09T14:18:23Zuvok2026-01-09T14:18:23Zurn:sha1:6c83fd8730e55de8b1daaac1deb111d3d9bd408emake: Use variables for suffixes2026-01-06T10:58:39Zuvok2026-01-06T10:58:39Zurn:sha1:11b3295acf4da3fd62a1cc2862e3e1b36bbf4c72fix verilator fuckup2026-01-01T17:37:29Zuvok2026-01-01T17:37:29Zurn:sha1:b2123214582fa715fac7ce9df4f15c3eb9a02c38
some recent version of verilator in oss-cad-build-suite
started adding_tb to the filename.
remove superfluous ws2026-01-01T14:32:35Zuvok2026-01-01T14:32:35Zurn:sha1:4792fb03e5d39da03633e71ff4b5375709bfb1d5linting, use different naming2025-12-30T09:21:27Zuvok2025-12-30T09:21:27Zurn:sha1:d0a372c3112b28ff3b1bf03ff4a7a0e5a3cafe8e
use _tb.v instead of .tb.v,
to stop verilator from shouting
the module name doesn't
match
make: shut up gtkwave2025-12-30T08:22:10Zuvok2025-12-30T08:22:10Zurn:sha1:6a46b79bd423648cd1b9e340216386250e55a2a4make,verilator: Use 4 make jobs2025-12-29T15:44:50Zuvok2025-12-29T15:44:50Zurn:sha1:0a4f9bf2fee4e5ebff9b797349e3a477a7013fdfmake: make verilator quiet2025-12-29T15:11:33Zuvok2025-12-29T15:11:33Zurn:sha1:ceb4aa8e0662206789016306a5a8745cbafcbd4fmake: Add rules for verilator simulation2025-12-28T13:01:42Zuvok2025-12-28T13:01:42Zurn:sha1:40245bbc8c364c4e1673332c9fcc243ede6dc264makefile: specify dumpfile on cmdline2025-12-28T12:44:05Zuvok2025-12-28T12:44:05Zurn:sha1:aa6519203d9af798acc9ed46d964705315b3b5d5