fpga-exper/nandgame/Makefile, branch mainFPGA experimentshttps://git.uvok.de/fpga-exper/atom?h=main2026-01-11T10:18:31Zfix olde makefile2026-01-11T10:18:31Zuvok2026-01-11T10:18:31Zurn:sha1:db6dbb0b71b0eeb299c105656b3e94952223b7f2Dumpfile on VERILATOR2026-01-11T09:32:31Zuvok2026-01-11T09:32:31Zurn:sha1:7a1fb3493197adcac3d285488d85fb9b494af2ed
get rid of VERILATE
Reorganize cpp files2026-01-11T09:14:34Zuvok2026-01-11T09:14:34Zurn:sha1:0f86e4c661fa3164447a77d84610146426008364verilator: Enable tracing2026-01-10T08:54:18Zuvok2026-01-09T18:36:14Zurn:sha1:acbeaa40a1580d85c1c4404f5f668b2b3059636dmake: Unified makefile2026-01-09T14:27:25Zuvok2026-01-09T14:27:25Zurn:sha1:ad413583bc71e1eb53f83f2ac3d1a5eb37fa8163makefile: Add instruction for simulated PC2026-01-08T18:41:10Zuvok2026-01-08T18:41:10Zurn:sha1:c2c1f652415cbe40bfffe6062fe41ddc3abebeafmake: Use variables for suffixes2026-01-06T10:58:39Zuvok2026-01-06T10:58:39Zurn:sha1:11b3295acf4da3fd62a1cc2862e3e1b36bbf4c72fix verilator fuckup2026-01-01T17:37:29Zuvok2026-01-01T17:37:29Zurn:sha1:b2123214582fa715fac7ce9df4f15c3eb9a02c38
some recent version of verilator in oss-cad-build-suite
started adding_tb to the filename.
don't delete vvp files2026-01-01T16:46:02Zuvok2026-01-01T16:46:02Zurn:sha1:54af62ca18ef8fabdd359dc6e855e33241dd4788Add arithmetic unit, disable gtkwave2026-01-01T14:44:40Zuvok2026-01-01T14:44:40Zurn:sha1:20fd019f0cf4c9110f44e46ff7820dd37598e164