fpga-exper/nandgame/cpp, branch main FPGA experiments https://git.uvok.de/fpga-exper/atom?h=main 2026-01-11T19:19:10Z verilator is required 2026-01-11T19:19:10Z uvok 2026-01-11T19:19:10Z urn:sha1:9b402d2bd6eb5d5d37e892d0066b2d2990341889 simpc: Rename define appropriately 2026-01-11T16:48:47Z uvok 2026-01-11T16:48:47Z urn:sha1:d29f372e404e2dece39fe103ff69d37d494e07d7 Go back to 1 tick per clock cycle 2026-01-11T16:47:59Z uvok 2026-01-11T16:47:59Z urn:sha1:a7f2820f1f2e62c1d51b800b7472c22b00267277 Fix resizing 2026-01-11T16:03:08Z uvok 2026-01-11T16:03:08Z urn:sha1:9e8ed43b6420d6bb1e50a140b394d5428d604fd1 Start in paused mode 2026-01-11T15:31:05Z uvok 2026-01-11T15:31:05Z urn:sha1:baf8a3f7991e60644a22cc384f3dd3baf4f2fc05 Add resize handler 2026-01-11T15:30:27Z uvok 2026-01-11T15:30:27Z urn:sha1:8bf039847599dd0828b42a83bd2addb6d0b28cf1 Draw borders around R[AO]M 2026-01-11T15:08:50Z uvok 2026-01-11T15:08:50Z urn:sha1:ab2df93f57b1f8439c8ac821ae7f9c3e64caeeed Use lots of windows 2026-01-11T15:06:02Z uvok 2026-01-11T15:06:02Z urn:sha1:15c2e473ea269a374fb5639c5a667a2f7d44c497 Fix pause logic 2026-01-11T15:05:43Z uvok 2026-01-11T15:05:43Z urn:sha1:02540b49d81bfaffcc7ff29ac8294f39db28f630 second p stuck Add ROM window 2026-01-11T14:42:25Z uvok 2026-01-11T14:42:25Z urn:sha1:f1a9c246e1a6293e97dcaca5f107c1cfec31112c