fpga-exper/playground, branch main
FPGA experiments
https://git.uvok.de/fpga-exper/atom?h=main
2026-01-16T17:22:36Z
(System)Verilog: Be explicit about wire/logic
2026-01-16T17:22:36Z
uvok
2026-01-16T17:22:10Z
urn:sha1:47c26f27b8be4c6c22ed81f701f1b25072bb3341
Remove rando int
2026-01-11T11:04:47Z
uvok
2026-01-10T16:11:55Z
urn:sha1:01927971ea09b25d12e946b000b27938341ef88c
mem: Add async data output
2026-01-11T11:00:00Z
uvok
2026-01-10T16:03:33Z
urn:sha1:50a1551a3f4df5da818cf04542ef2a74dc97ed3e
make: Unified makefile
2026-01-09T14:27:25Z
uvok
2026-01-09T14:27:25Z
urn:sha1:ad413583bc71e1eb53f83f2ac3d1a5eb37fa8163
move stuff around
2026-01-09T14:18:23Z
uvok
2026-01-09T14:18:23Z
urn:sha1:6c83fd8730e55de8b1daaac1deb111d3d9bd408e