fifo: r/w/address logic

2 files changed, 53 insertions, 9 deletions

diff --git a/fifo.tb.v b/fifo.tb.v
index b948cf1..6556eca 100644
--- a/fifo.tb.v
+++ b/fifo.tb.v
@@ -6,9 +6,18 @@ module fifo_tb (
 reg clk_i;
 reg rst_i;
 
-fifo uut(
+reg read_i, write_i;
+reg [7:0] data_i;
+
+fifo #(
+  .DATA_WIDTH(8),
+  .DATA_DEPTH(8)
+) uut(
   .clk_i(clk_i),
-  .rst_i(rst_i)
+  .rst_i(rst_i),
+  .write_i(write_i),
+  .read_i(read_i),
+  .data_i
 );
 
 string filename;
@@ -21,12 +30,38 @@ initial begin
   $dumpfile(filename); $dumpvars();
   clk_i <= 0;
   rst_i <= 1'b1;
-
+  read_i = 0;
+  write_i = 0;
+  data_i = 0;
 end
 
 always #10 clk_i = ~clk_i;
 
 initial begin
+  #10
+
+  for (integer run = 0; run < 2; run++) begin
+  
+    write_i = 1;
+    for (integer addr = 0; addr < 10; addr++) begin
+
+      data_i = addr + run;
+      #20
+      ;
+    end
+
+    write_i = 0;
+    read_i = 1;
+
+    for (integer addr = 0; addr < 10; addr++) begin
+      #20
+      ;
+    end
+
+    read_i = 0;
+    #20
+    ;
+  end
   #100
   $finish();
 end
diff --git a/fifo.v b/fifo.v
index 43410e1..5e7a826 100644
--- a/fifo.v
+++ b/fifo.v
@@ -1,6 +1,6 @@
 module fifo #(
   parameter DATA_WIDTH = 8,
-  parameter DATA_DEPTH = 8
+  parameter DATA_DEPTH = 1024
 ) (
   input rst_i,
   input clk_i,
@@ -11,14 +11,15 @@ module fifo #(
   output empty_o,
   output full_o,
 
-  output data_valid_o,
+  //output data_valid_o,
 
   input [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o
 
 );
 
-reg [$clog2(DATA_DEPTH)-1:0] r_count;
+// need to "count" to number *including* depth
+reg [$clog2(DATA_DEPTH + 1)-1:0] r_count;
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];
 reg [$clog2(DATA_DEPTH)-1:0] r_read_addr;
 reg [$clog2(DATA_DEPTH)-1:0] r_write_addr;
@@ -39,15 +40,23 @@ always @(posedge clk_i or negedge rst_i) begin
   end else if (write_i && !full_o) begin
     r_count <= r_count + 1;
     r_datastore[r_write_addr] <= data_i;
-    r_write_addr <= (r_write_addr < (DATA_DEPTH - 1) ? r_write_addr + 1 : 0);
+    // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does?
+    if ({1'b0, r_write_addr} < (DATA_DEPTH - 1))
+      r_write_addr <= r_write_addr + 1;
+    else
+      r_write_addr <= 0;
   end else if (read_i && !empty_o) begin
     r_count <= r_count - 1;
     data_o <= r_datastore[r_read_addr];
-    r_read_addr <= (r_read_addr < (DATA_DEPTH - 1) ? r_read_addr + 1 : 0);
+    // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does?
+    if ({1'b0, r_read_addr} < (DATA_DEPTH - 1))
+      r_read_addr <= r_read_addr + 1;
+    else
+      r_read_addr <= 0;
   end
 end
 
 assign empty_o = r_count == 0;
-assign full_o = r_count >= DATA_DEPTH - 1;
+assign full_o = r_count == DATA_DEPTH;
 
 endmodule