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authoruvok2025-12-26 18:17:44 +0100
committeruvok2025-12-26 18:17:44 +0100
commit36d351f4e07635a806d5ca67749fa6fb46db810f (patch)
tree408630c0c6e8f92447ba8fe2d9607396a17001de
parent0846857a7e8ac4bef959ecf09ee5fa3ffc24991f (diff)
continue complaining
-rw-r--r--par_to_ser.v3
-rw-r--r--ser_to_par.v4
2 files changed, 5 insertions, 2 deletions
diff --git a/par_to_ser.v b/par_to_ser.v
index 5e261a9..b3a8eb0 100644
--- a/par_to_ser.v
+++ b/par_to_ser.v
@@ -18,7 +18,8 @@ reg [7:0] send_data = 8'hff;
// Learning:
// Ugh, this is fucking stupid.
// if I send out directly at the rising clock edge,
-// the output will violate setup and hold times???
+// the output, when directly used again with the same clock,
+// will violate setup and hold times???
//
always @(posedge clk_i or negedge rst_i) begin
diff --git a/ser_to_par.v b/ser_to_par.v
index 14ac831..fc6d22f 100644
--- a/ser_to_par.v
+++ b/ser_to_par.v
@@ -2,6 +2,7 @@
// Learning:
// I don't like this.
// I think I need a signal / way to say "I'm finished"?
+// or generally, an enable pin.
//
module ser_to_par (
@@ -14,7 +15,8 @@ module ser_to_par (
// Learning:
// Ugh, this is fucking stupid.
// if I send out directly at the rising clock edge,
-// the output will violate setup and hold times???
+// the output, when directly used again with the same clock,
+// will violate setup and hold times???
//
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin