(System)Verilog: Be explicit about wire/logic

25 files changed, 107 insertions, 107 deletions

diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
index bbe7a0c..fe34202 100644
--- a/eater_cpu/bus_writer.sv
+++ b/eater_cpu/bus_writer.sv
@@ -3,9 +3,9 @@
 `timescale 1us/1us
 
 module bus_writer (
-    input [7:0] in_value,
-    input in_write_to_output,
-    output [7:0] out_value
+    input wire [7:0] in_value,
+    input wire in_write_to_output,
+    output wire [7:0] out_value
 );
 
 assign out_value = in_write_to_output ? in_value : 8'bZ;
diff --git a/eater_cpu/eater_alu.sv b/eater_cpu/eater_alu.sv
index bbfb050..1474d6d 100644
--- a/eater_cpu/eater_alu.sv
+++ b/eater_cpu/eater_alu.sv
@@ -3,15 +3,15 @@
 `timescale 1us/1us
 
 module eater_alu (
-    input clk_in,
-    input en_output_in,
+    input wire clk_in,
+    input wire en_output_in,
 
-    input subtract_n_add_in,
+    input wire subtract_n_add_in,
 
-    input [7:0] A_in,
-    input [7:0] B_in,
+    input wire [7:0] A_in,
+    input wire [7:0] B_in,
 
-    output [7:0] bus_out
+    output wire [7:0] bus_out
 );
 
 wire [7:0] result = subtract_n_add_in ? (A_in - B_in) : (A_in + B_in);
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 52c53a4..22b8f4f 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -6,16 +6,16 @@
 module eater_register #(
   parameter DATA_WIDTH = 8
 ) (
-  input clk_in,
+  input wire clk_in,
 
   // store data on rising clk?
-  input en_store_in,
+  input wire en_store_in,
   // async - output data to bus
-  input en_output_in,
+  input wire en_output_in,
 
-  input [(DATA_WIDTH-1) : 0] data_in,
-  output [(DATA_WIDTH-1) : 0] bus_out,
-  output [(DATA_WIDTH-1) : 0] always_out
+  input wire [(DATA_WIDTH-1) : 0] data_in,
+  output wire [(DATA_WIDTH-1) : 0] bus_out,
+  output wire [(DATA_WIDTH-1) : 0] always_out
   // inout [(DATA_WIDTH-1) : 0] data
   
 );
diff --git a/nandgame/alu.sv b/nandgame/alu.sv
index 54297c9..5f82a64 100644
--- a/nandgame/alu.sv
+++ b/nandgame/alu.sv
@@ -13,17 +13,17 @@ module  alu #(
   parameter DATA_WIDTH = 16
 ) (
   // "X" operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // "Y" operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // "u" flag. 1=arithmetic, 0=logic operation
-  input logic u_arith_nlogic_in,
+  input wire u_arith_nlogic_in,
   // opcode, see ArithCode / LogicCode
-  input logic [1:0] opcode_in,
+  input wire [1:0] opcode_in,
   // zero the "X" operand
-  input logic zx_in,
+  input wire zx_in,
   // swap "X" and "Y" operands
-  input logic sw_in,
+  input wire sw_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
diff --git a/nandgame/arith_unit.sv b/nandgame/arith_unit.sv
index 53ea17e..75736ab 100644
--- a/nandgame/arith_unit.sv
+++ b/nandgame/arith_unit.sv
@@ -11,11 +11,11 @@ module  arith_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see ArithCode
-  input ArithCode arith_operation_in,
+  input wire ArithCode arith_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv
index b68fc22..a095f81 100644
--- a/nandgame/comb_mem.sv
+++ b/nandgame/comb_mem.sv
@@ -13,23 +13,23 @@ module comb_mem #(
   parameter DATA_WIDTH = 16
 ) (
     // store to A register
-    input store_to_a_in,
+    input wire store_to_a_in,
     // store to D register
-    input store_to_d_in,
+    input wire store_to_d_in,
     // store to address in memory pointed to by A (currently)
-    input store_to_pa_in,
+    input wire store_to_pa_in,
 
     // value to store
-    input [(DATA_WIDTH-1):0] X_in,
+    input wire [(DATA_WIDTH-1):0] X_in,
     // output registers updated on falling edge
     input wire clk_in,
 
     // content of A register
-    output reg [(DATA_WIDTH-1):0] reg_A_out,
+    output logic [(DATA_WIDTH-1):0] reg_A_out,
     // content of D register
-    output reg [(DATA_WIDTH-1):0] reg_D_out,
+    output logic [(DATA_WIDTH-1):0] reg_D_out,
     // content memory pointed to by A register
-    output reg [(DATA_WIDTH-1):0] reg_pA_out
+    output logic [(DATA_WIDTH-1):0] reg_pA_out
 );
 
 wire inv_clk_int;
diff --git a/nandgame/computer.sv b/nandgame/computer.sv
index 5c2127f..3286bfe 100644
--- a/nandgame/computer.sv
+++ b/nandgame/computer.sv
@@ -8,8 +8,8 @@
 `include "counter.sv"
 
 module computer (
-  input clk_in,
-  output halt
+  input wire clk_in,
+  output wire halt
 );
 
 wire nclk_int;
diff --git a/nandgame/cond_check.sv b/nandgame/cond_check.sv
index 3961313..6aa8289 100644
--- a/nandgame/cond_check.sv
+++ b/nandgame/cond_check.sv
@@ -9,7 +9,7 @@ module  cond_check #(
   parameter DATA_WIDTH = 16
 ) (
   // operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // check whether operand < 0
   input wire check_ltz_in,
   // check whether operand == 0
diff --git a/nandgame/counter.sv b/nandgame/counter.sv
index 90afa9b..2089194 100644
--- a/nandgame/counter.sv
+++ b/nandgame/counter.sv
@@ -9,7 +9,7 @@ module  counter #(
   parameter DATA_WIDTH = 16
 ) (
   // input / value to store in counter
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // whether to store input (else increment)
   input wire st_store_X_in,
   // clock
diff --git a/nandgame/hack_alu.sv b/nandgame/hack_alu.sv
index 93d7476..94e30b9 100644
--- a/nandgame/hack_alu.sv
+++ b/nandgame/hack_alu.sv
@@ -10,24 +10,24 @@ module  alu #(
   parameter DATA_WIDTH = 16
 ) (
   // "X" operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // "Y" operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
 
   // zero X
-  input zx,
+  input wire zx,
   // negate X
-  input nx,
+  input wire nx,
   // zero Y
-  input zy,
+  input wire zy,
   // negate Y
-  input ny,
+  input wire ny,
 
   // "u" flag. 1=add, 0=and
-  input logic f_arith_nlogic_in,
+  input wire f_arith_nlogic_in,
 
   // negate output
-  input logic neg_out,
+  input wire neg_out,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out,
diff --git a/nandgame/instruction_decode.sv b/nandgame/instruction_decode.sv
index b78bee8..4cd7e97 100644
--- a/nandgame/instruction_decode.sv
+++ b/nandgame/instruction_decode.sv
@@ -15,28 +15,28 @@ module instruction_decode  #(
   parameter DATA_WIDTH = 16
 ) (
   // instruction to decode
-  input [15:0] instruction_in,
+  input wire [15:0] instruction_in,
   
   // value of A register
-  input [(DATA_WIDTH-1):0] A_in,
+  input wire [(DATA_WIDTH-1):0] A_in,
   // value of D register
-  input [(DATA_WIDTH-1):0] D_in,
+  input wire [(DATA_WIDTH-1):0] D_in,
   // content of memory at address in A register
-  input [(DATA_WIDTH-1):0] pA_in,
+  input wire [(DATA_WIDTH-1):0] pA_in,
   
   // result of operation
-  output [(DATA_WIDTH-1):0] result_out,
+  output wire [(DATA_WIDTH-1):0] result_out,
   // whether a jump should occur
-  output do_jump_out,
+  output wire do_jump_out,
 
   // whether result should be stored to A
-  output dst_A_out,
+  output wire dst_A_out,
   // whether result should be stored to D
-  output dst_D_out,
+  output wire dst_D_out,
   // whether result should be stored in memory at address in A register
-  output dst_pA_out,
+  output wire dst_pA_out,
   // Invalid instruction
-  output invalid_ins
+  output wire invalid_ins
 );
 
 wire is_immediate_int;
diff --git a/nandgame/logic_unit.sv b/nandgame/logic_unit.sv
index 68f5c23..9207806 100644
--- a/nandgame/logic_unit.sv
+++ b/nandgame/logic_unit.sv
@@ -11,11 +11,11 @@ module logic_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see LogicCode
-  input LogicCode logic_operation_in,
+  input wire LogicCode logic_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
diff --git a/playground/clkdiv.v b/playground/clkdiv.v
index b6f1419..442ff35 100644
--- a/playground/clkdiv.v
+++ b/playground/clkdiv.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module clkdiv (
-    input rst_i,
-    input clk,              // clk input
+    input wire rst_i,
+    input wire clk,              // clk input
     output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
 );
 
diff --git a/playground/debounce.v b/playground/debounce.v
index 33dc22e..4c68e2e 100644
--- a/playground/debounce.v
+++ b/playground/debounce.v
@@ -1,9 +1,9 @@
 `timescale 1us/1us
 
 module debounce (
-  input rst_i,
-  input clk_i,
-  input signal_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire signal_i,
   output reg signal_o
 );
 
diff --git a/playground/fifo.v b/playground/fifo.v
index bcc2d3f..a239069 100644
--- a/playground/fifo.v
+++ b/playground/fifo.v
@@ -6,18 +6,18 @@ module fifo #(
   parameter DATA_WIDTH = 8,
   parameter DATA_DEPTH = 1024
 ) (
-  input rst_i,
-  input clk_i,
+  input wire rst_i,
+  input wire clk_i,
 
-  input write_i,
-  input read_i,
+  input wire write_i,
+  input wire read_i,
 
-  output empty_o,
-  output full_o,
+  output wire empty_o,
+  output wire full_o,
 
   //output data_valid_o,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
+  input wire [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o
 
 );
diff --git a/playground/fizzbuzz.v b/playground/fizzbuzz.v
index 0e34c58..d251198 100644
--- a/playground/fizzbuzz.v
+++ b/playground/fizzbuzz.v
@@ -1,11 +1,11 @@
 `timescale 1us/1us
 
 module fizzbuzz (
-  input [7:0] num_i,
-  output [7:0] num_o,
-  output fizz_o,
-  output buzz_o,
-  output fizzbuzz_o
+  input wire [7:0] num_i,
+  output wire [7:0] num_o,
+  output wire fizz_o,
+  output wire buzz_o,
+  output wire fizzbuzz_o
 );
 
 wire is_fizz, is_buzz;
diff --git a/playground/led.v b/playground/led.v
index e4f4281..bf402d2 100644
--- a/playground/led.v
+++ b/playground/led.v
@@ -3,8 +3,8 @@
 `include "clkdiv.v"
 
 module led (
-    input clk,              // clk input
-    input rst_i,              // reset input
+    input wire clk,              // clk input
+    input wire rst_i,              // reset input
     output reg [5:0] led_o    // 6 LEDS pin
 );
 
diff --git a/playground/led_toggle.v b/playground/led_toggle.v
index 3c54ee4..f26d3be 100644
--- a/playground/led_toggle.v
+++ b/playground/led_toggle.v
@@ -7,10 +7,10 @@
 `include "debounce.v"
 
 module led_toggle (
-  input rst_i,
-  input clk_i,
-  input key_i,
-  output [5:0] led
+  input wire rst_i,
+  input wire clk_i,
+  input wire key_i,
+  output wire [5:0] led
 );
 parameter STABLE_PERIOD = 50;
 
diff --git a/playground/led_toggle_bouncy.v b/playground/led_toggle_bouncy.v
index b05b472..8e783f2 100644
--- a/playground/led_toggle_bouncy.v
+++ b/playground/led_toggle_bouncy.v
@@ -4,9 +4,9 @@
 // bouncy variant
 
 module led_toggle_bouncy (
-  input clk_i,
-  input key_i,
-  output [5:0] led
+  input wire clk_i,
+  input wire key_i,
+  output wire [5:0] led
 );
 
 reg r_LED_1 = 1'b1;
diff --git a/playground/led_toggle_nonwork.v b/playground/led_toggle_nonwork.v
index 5fe458f..2450ce4 100644
--- a/playground/led_toggle_nonwork.v
+++ b/playground/led_toggle_nonwork.v
@@ -7,9 +7,9 @@
 //
 
 module led_toggle_nonwork(
-  input clk_i,
-  input key_i,
-  input rst_i,
+  input wire clk_i,
+  input wire key_i,
+  input wire rst_i,
   output reg [5:0] led
 );
 
diff --git a/playground/my_mem.v b/playground/my_mem.v
index ebffcb8..b472c1e 100644
--- a/playground/my_mem.v
+++ b/playground/my_mem.v
@@ -7,17 +7,17 @@ module my_mem #(
   parameter DATA_WIDTH = 8,
   parameter DATA_DEPTH = 1024
 ) (
-  input clk_i,
+  input wire clk_i,
 
-  input write_en_i,
-  input read_en_i,
+  input wire write_en_i,
+  input wire read_en_i,
 
-  input [$clog2(DATA_DEPTH)-1:0] r_read_addr,
-  input [$clog2(DATA_DEPTH)-1:0] r_write_addr,
+  input wire [$clog2(DATA_DEPTH)-1:0] r_read_addr,
+  input wire [$clog2(DATA_DEPTH)-1:0] r_write_addr,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
+  input wire [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o,
-  output [(DATA_WIDTH-1) : 0] async_data_o
+  output wire [(DATA_WIDTH-1) : 0] async_data_o
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;
diff --git a/playground/par_to_ser.v b/playground/par_to_ser.v
index ab754c9..677f70b 100644
--- a/playground/par_to_ser.v
+++ b/playground/par_to_ser.v
@@ -5,12 +5,12 @@
 module par_to_ser #(
   parameter SHIFT_WIDTH = 8
 ) (
-  input rst_i,
-  input clk_i,
-  input data_valid_i,
-  input [(SHIFT_WIDTH-1):0] dat_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire data_valid_i,
+  input wire [(SHIFT_WIDTH-1):0] dat_i,
   output reg dat_o,
-  output dat_valid_o
+  output wire dat_valid_o
 );
 
 // Learning: can't declate parameter here
diff --git a/playground/ser_to_par.v b/playground/ser_to_par.v
index f0a0c47..edb05df 100644
--- a/playground/ser_to_par.v
+++ b/playground/ser_to_par.v
@@ -10,15 +10,15 @@
 module ser_to_par #(
   parameter SHIFT_WIDTH = 8
 ) (
-  input rst_i,
-  input clk_i,
+  input wire rst_i,
+  input wire clk_i,
 
-  input dat_valid_i,
-  input dat_i,
+  input wire dat_valid_i,
+  input wire dat_i,
 
-  output reg[(SHIFT_WIDTH - 1):0] dat_o,
+  output reg [(SHIFT_WIDTH - 1):0] dat_o,
   // ???
-  output dat_valid_o
+  output wire dat_valid_o
 );
 
 reg [$clog2(SHIFT_WIDTH) - 1 : 0] count = {$clog2(SHIFT_WIDTH){1'b0}};
diff --git a/playground/template.v b/playground/template.v
index e6f5280..2cbe671 100644
--- a/playground/template.v
+++ b/playground/template.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module template (
-  input rst_i,
-  input clk_i
+  input wire rst_i,
+  input wire clk_i
 );
 
 always @(posedge clk_i or negedge rst_i) begin
diff --git a/playground/tst_delay.v b/playground/tst_delay.v
index c4017bd..6d2c420 100644
--- a/playground/tst_delay.v
+++ b/playground/tst_delay.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module tst_delay (
-  input clk_i,
-  input data_i,
+  input wire clk_i,
+  input wire data_i,
   output reg data_o
 );