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| author | uvok | 2025-12-28 15:46:44 +0100 |
|---|---|---|
| committer | uvok | 2025-12-28 15:46:44 +0100 |
| commit | 6efd8dd08d75235a58e1da38f292728a439c9df5 (patch) | |
| tree | 19c9e34d5ca6613448984e1cd1c354598c55a3e5 | |
| parent | 740a9037cddaadcb14168e01fe88ee33d07ea8f5 (diff) | |
p2s: Add valid output signal
| -rw-r--r-- | par_to_ser.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/par_to_ser.v b/par_to_ser.v index 8c814c4..e817608 100644 --- a/par_to_ser.v +++ b/par_to_ser.v @@ -7,7 +7,8 @@ module par_to_ser #( input clk_i, input data_valid_i, input [(SHIFT_WIDTH-1):0] dat_i, - output reg dat_o + output reg dat_o, + output dat_valid_o ); // Learning: can't declate parameter here @@ -56,4 +57,6 @@ always @(posedge clk_i or negedge rst_i) begin end end +assign dat_valid_o = sending; + endmodule |
