eater: Extract computer testbench

2 files changed, 84 insertions, 57 deletions

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index 171e012..9595abf 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -3,9 +3,9 @@
 `timescale 1us/1us
 
 module eater_computer(
+  input clk_in,
   output [7:0] debug_bus
 );
-logic clk_in;
 
 /* verilator public_on */
 tri [7:0] bus, A_out, B_out;
@@ -56,63 +56,8 @@ eater_alu alu (
   .en_output_in(ALU_to_bus),
   .A_in(A_out),
   .B_in(B_out),
-  .subtract_n_add_in(0),
+  .subtract_n_add_in(1'b0),
   .bus_out(bus)
 );
 
-`ifdef VERILATOR
-
-logic [7:0] debug_value;
-logic debug_enable;
-
-bus_writer debugger (
-  .in_value(debug_value),
-  .in_write_to_output(debug_enable),
-  .out_value(bus)
-);
-
-initial begin
-  $dumpfile("simpc.vvp");
-  $dumpvars();
-
-  A_to_bus = 0;
-  B_to_bus = 0;
-  INS_to_bus = 0;
-  bus_to_A = 0;
-  bus_to_B = 0;
-  bus_to_INS = 0;
-  clk_in = 0;
-  debug_enable = 0;
-  debug_value = 'z;
-end
-
-always #2 clk_in = ~clk_in;
-
-initial begin
-
-  @(negedge clk_in);
-  debug_value = 'haa;
-  debug_enable = 1;
-
-  bus_to_A = 1;
-  @(negedge clk_in);
-  bus_to_A = 0;
-  debug_value = 'hbb;
-  bus_to_B = 1;
-  @(negedge clk_in);
-  bus_to_B = 0;
-  debug_value = 'hcc;
-  bus_to_INS = 1;
-  @(negedge clk_in);
-  debug_enable = 0;
-  debug_value = 'z;
-  bus_to_INS = 0;
-  @(negedge clk_in);
-  A_to_bus = 1;
-  @(negedge clk_in);
-  #10
-  $finish();
-end
-`endif
-
 endmodule
diff --git a/eater_cpu/eater_computer_tb.sv b/eater_cpu/eater_computer_tb.sv
new file mode 100644
index 0000000..5739dc0
--- /dev/null
+++ b/eater_cpu/eater_computer_tb.sv
@@ -0,0 +1,82 @@
+// represents the Ben Eater 8bit computer
+
+`timescale 1us/1us
+
+module eater_computer_tb;
+
+logic clk_in;
+
+eater_computer uut (
+  .debug_bus(),
+  .clk_in(clk_in)
+);
+
+logic [7:0] debug_value;
+logic debug_enable;
+
+bus_writer debugger (
+  .in_value(debug_value),
+  .in_write_to_output(debug_enable),
+  .out_value(uut.bus)
+);
+
+initial begin
+  $dumpfile("simpc.vvp");
+  $dumpvars();
+
+  uut.A_to_bus = 0;
+  uut.B_to_bus = 0;
+  uut.INS_to_bus = 0;
+  uut.ALU_to_bus = 0;
+  uut.bus_to_A = 0;
+  uut.bus_to_B = 0;
+  uut.bus_to_INS = 0;
+  clk_in = 0;
+  debug_enable = 0;
+  debug_value = 'z;
+end
+
+always #2 clk_in = ~clk_in;
+
+initial begin
+
+  @(negedge clk_in);
+  debug_value = 'haa;
+  debug_enable = 1;
+  uut.bus_to_A = 1;
+
+  @(negedge clk_in);
+  uut.bus_to_A = 0;
+  debug_value = 'hbb;
+  uut.bus_to_B = 1;
+
+  @(negedge clk_in);
+  uut.bus_to_B = 0;
+  debug_value = 'hcc;
+  uut.bus_to_INS = 1;
+
+  @(negedge clk_in);
+  debug_enable = 0;
+  debug_value = 'z;
+  uut.bus_to_INS = 0;
+
+  @(negedge clk_in);
+  uut.A_to_bus = 1;
+
+  @(negedge clk_in);
+  assert (uut.bus == 'haa) 
+  else   $error("Expected 0xaa, got 0x%02x on bus", uut.bus);
+  uut.A_to_bus = 0;
+
+  @(negedge clk_in);
+  uut.ALU_to_bus = 1;
+
+  @(negedge clk_in);
+  assert (uut.bus == 8'('haa + 'hbb))
+  else   $error("Expected 0x%02x, got 0x%02x on bus", 8'('haa + 'hbb), uut.bus);
+
+  #10
+  $finish();
+end
+
+endmodule