Make clock divider separate module

2 files changed, 46 insertions, 14 deletions

diff --git a/clkdiv.v b/clkdiv.v
new file mode 100644
index 0000000..aef93eb
--- /dev/null
+++ b/clkdiv.v
@@ -0,0 +1,31 @@
+module clkdiv (
+    input rst_i,
+    input clk,              // clk input
+    output o_divclk
+);
+
+reg [23:0] counter;
+
+always @(posedge clk or negedge rst_i) begin
+    if (!rst_i)
+        counter <= 24'd0;
+//    else if (counter < 24'd1349_9999)       // 0.5s delay
+    else if (counter < 24'd674_9999)       // 0.5s delay
+        counter <= counter + 1'b1;
+    else
+        counter <= 24'd0;
+end
+
+always @(posedge clk or negedge rst_i) begin
+    if (!rst_i)
+        o_divclk <= 1'b0;
+//    else if (counter == 24'd1349_9999)       // 0.5s delay
+    else if (counter == 24'd674_9999)       // 0.5s delay
+        o_divclk[0] <= o_divclk[0] + 1;
+    else
+        o_divclk <= o_divclk;
+end
+
+
+endmodule
+
diff --git a/led.v b/led.v
index 772415f..e99e5ba 100644
--- a/led.v
+++ b/led.v
@@ -1,28 +1,29 @@
+`include "clkdiv.v"
+
 module led (
     input clk,              // clk input
     input rst_i,              // reset input
     output reg [5:0] led    // 6 LEDS pin
 );
 
-reg [23:0] counter;
+wire myclk;
 
-always @(posedge clk or negedge rst_i) begin
-    if (!rst_i)
-        counter <= 24'd0;
-    else if (counter < 24'd1349_9999)       // 0.5s delay
-        counter <= counter + 1'b1;
-    else
-        counter <= 24'd0;
-end
+clkdiv bla(
+  .rst_i(rst_i),
+  .clk(clk),
+  .o_divclk(myclk)
+);
 
-always @(posedge clk or negedge rst_i) begin
+always @(posedge myclk or negedge rst_i) begin
     if (!rst_i)
-        led <= 6'b111110;
-    else if (counter == 24'd1349_9999)       // 0.5s delay
-        led[5:0] <= led[5:0] - 1;
+        led <= 6'b011110;
     else
-        led <= led;
+//    else if (counter == 24'd1349_9999)       // 0.5s delay
+        led[5:0] <= led[5:0] - 1;
+//    else
+//        led <= led;
 end
 
+
 endmodule