diff options
| author | uvok | 2026-01-05 18:50:10 +0100 |
|---|---|---|
| committer | uvok | 2026-01-05 18:50:10 +0100 |
| commit | aad3b7aa0732cf127b1a44ff956e9447cbf9afef (patch) | |
| tree | 7bc9736a1ef18d676297abc79af3938a2024d9fb | |
| parent | c1fdbef01ff06d4d9b518b360ecc1890a17d4c21 (diff) | |
mem: output current value only for DEBUG
| -rw-r--r-- | my_mem.v | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -20,20 +20,27 @@ module my_mem #( ); reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0]; + +`ifdef DEBUG // for debugging simulations, as iverilog // does't show r_datastore reg [(DATA_WIDTH-1) : 0] r_cur_r_val; reg [(DATA_WIDTH-1) : 0] r_cur_w_val; +`endif always @(posedge clk_i) begin if (write_en_i) begin r_datastore[r_write_addr] <= data_i; +`ifdef DEBUG r_cur_w_val <= data_i; +`endif end if (read_en_i) begin data_o <= r_datastore[r_read_addr]; +`ifdef DEBUG r_cur_r_val <= r_datastore[r_read_addr]; +`endif end end |
