p2s2p: Fix testbench

iverilog syntax error (needs space)
timing
use logic,

1 files changed, 26 insertions, 23 deletions

diff --git a/par_to_ser_to_ser.tb.v b/par_to_ser_to_par.tb.v
index 1f30ae2..c422d86 100644
--- a/par_to_ser_to_ser.tb.v
+++ b/par_to_ser_to_par.tb.v
@@ -3,19 +3,19 @@
 
 `timescale 1us/1us
 
-module par_to_ser_tb (
+module par_to_ser_to_par_tb (
 );
 
-reg clk_i;
-reg rst_i;
-reg data_valid_i;
-reg [7:0] dat_i;
-wire dat_o;
-wire [7:0] dat_o2;
+logic clk_i;
+logic rst_i;
+logic data_valid_i;
+logic [7:0] dat_i;
 
-wire send_valid;
+logic dat_o;
+logic [7:0] dat_o2;
+logic send_valid;
 
-par_to_ser uut(
+par_to_ser uut (
   .clk_i(clk_i),
   .rst_i(rst_i),
   .data_valid_i(data_valid_i),
@@ -24,7 +24,7 @@ par_to_ser uut(
   .dat_valid_o(send_valid)
 );
 
-ser_to_par uut2(
+ser_to_par uut2 (
   .clk_i(clk_i),
   .rst_i(rst_i),
 
@@ -40,36 +40,39 @@ initial begin
 `ifdef DUMP_FILE_NAME
   filename=`DUMP_FILE_NAME;
 `else
-  filename="par_to_ser.lxt2";
+  filename="par_to_ser_to_par.lxt2";
 `endif
   $dumpfile(filename); $dumpvars();
-  clk_i <= 0;
-  rst_i <= 1'b1;
-  data_valid_i <= 1'b0;
+  clk_i = 0;
+  rst_i = 1'b1;
+  data_valid_i = 1'b0;
 
   #1
-  rst_i <= 1'b0;
+  rst_i = 1'b0;
   #1
-  rst_i <= 1'b1;
+  rst_i = 1'b1;
 end
 
 always #10 clk_i = ~clk_i;
 
 initial begin
-  #37
+  #13;
+  @(negedge clk_i);
 
   for (integer i = 0; i < 255; i++) begin
     // clock data in
-    dat_i <= i;
-    data_valid_i <= 1'b1;
+    dat_i = i;
+    data_valid_i = 1'b1;
 
     // wait 1 cycle
-    #20
-    data_valid_i <= 1'b0;
+    @(negedge clk_i);
+    data_valid_i = 1'b0;
 
     // let module do its work
-    #200
-    assert(i == dat_o2);
+    repeat(10) @(negedge clk_i);
+  
+    assert(i == dat_o2)
+    else $error("Expected output to be h%x, but was h%x", i, dat_o2);
 
   end