make: Add rules for verilator simulation

1 files changed, 15 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index 9e0aae7..f6aa04b 100644
--- a/Makefile
+++ b/Makefile
@@ -53,6 +53,9 @@ clean:
 simu: $(PROGRAM).lxt2
 	gtkwave $<
 
+simu2: verilator.$(PROGRAM)/dump.vvp
+	gtkwave $<
+
 lint: $(PROGRAM).v
 	verilator --lint-only -Wall -Wno-PROCASSINIT $(PROGRAM).v
 
@@ -96,6 +99,18 @@ lint: $(PROGRAM).v
 %.vvp: %.v %.tb.v
 	iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*.tb.v
 
+# verilog unfortunately exits on any warning
+# also on warnings "boohoo, you specified timings in some modules and not in others"
+# since this is fucking annoying, I choose to ignore the exit code.
+verilator.%: %.v %.tb.v
+	verilator -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(PROGRAM) $(PROGRAM).tb.v || true
+
+# need to specify RM for some reason
+# verilators makefiles doesn't specify the variable
+verilator.%/dump.vvp: verilator.%
+	$(MAKE) -C verilator.$(*) -f V$(*).mk RM=rm
+	cd verilator.$(*) && ./V$(*)
+
 ## inter-file dependencies
 -include $(DEPS)
 -include $($(wildcard *.fs:.fs=.dep)