diff options
| author | uvok | 2025-12-24 19:36:32 +0100 |
|---|---|---|
| committer | uvok | 2025-12-24 19:36:32 +0100 |
| commit | 4e9cc716642407a030c32354b58a30b9065722ca (patch) | |
| tree | 26068206e544faa29f4ceafacfb4ec5acb3ac2c0 /clkdiv.v | |
| parent | 157a4074b3ffaf80564bba1cf74f3b25c87ee6c5 (diff) | |
Use localparam for divisor
Diffstat (limited to 'clkdiv.v')
| -rw-r--r-- | clkdiv.v | 10 |
1 files changed, 7 insertions, 3 deletions
@@ -5,12 +5,16 @@ module clkdiv ( ); reg [23:0] counter; +// CLK is 27 MHz +// we want a 2Hz signal at the output +// and pin needs to *toggle twice* within one period +// 27MHz / 4 = 6750000 +localparam DIVISOR = 24'd6_749_999; always @(posedge clk or negedge rst_i) begin if (!rst_i) counter <= 24'd0; -// else if (counter < 24'd1349_9999) // 0.5s delay - else if (counter < 24'd674_9999) // 0.5s delay + else if (counter < DIVISOR) counter <= counter + 1'b1; else counter <= 24'd0; @@ -19,7 +23,7 @@ end always @(posedge clk or negedge rst_i) begin if (!rst_i) o_divclk <= 1'b0; - else if (counter == 24'd674_9999) // 0.5s delay + else if (counter == DIVISOR) o_divclk <= ~o_divclk; else o_divclk <= o_divclk; |
