clkdiv: output must be a register

1 files changed, 2 insertions, 3 deletions

diff --git a/clkdiv.v b/clkdiv.v
index aef93eb..7cf6cc3 100644
--- a/clkdiv.v
+++ b/clkdiv.v
@@ -1,7 +1,7 @@
 module clkdiv (
     input rst_i,
     input clk,              // clk input
-    output o_divclk
+    output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
 );
 
 reg [23:0] counter;
@@ -19,9 +19,8 @@ end
 always @(posedge clk or negedge rst_i) begin
     if (!rst_i)
         o_divclk <= 1'b0;
-//    else if (counter == 24'd1349_9999)       // 0.5s delay
     else if (counter == 24'd674_9999)       // 0.5s delay
-        o_divclk[0] <= o_divclk[0] + 1;
+        o_divclk <= ~o_divclk;
     else
         o_divclk <= o_divclk;
 end