diff options
| author | uvok | 2025-12-26 14:50:22 +0100 |
|---|---|---|
| committer | uvok | 2025-12-26 14:50:22 +0100 |
| commit | c756a4d5b920602873a938a7adde6f626e2199b0 (patch) | |
| tree | 9fe400a0effe1af986ee70d08e73caae39f9e2b1 /debounce.v | |
| parent | 35210703cb1fbd3d45365b22f425cc84ea630c90 (diff) | |
debounde: implement
using params
Diffstat (limited to 'debounce.v')
| -rw-r--r-- | debounce.v | 32 |
1 files changed, 30 insertions, 2 deletions
@@ -5,11 +5,39 @@ module debounce ( output reg signal_o ); +parameter STABLE_PERIOD = 50; +parameter INIT_SIG_STATE = 1'b1; + +reg [31:0] clk_counter; +reg prev_state; + always @(posedge clk_i or negedge rst_i) begin if (!rst_i) begin - + clk_counter <= 0; + prev_state <= INIT_SIG_STATE; + signal_o <= INIT_SIG_STATE; + end else begin + clk_counter <= clk_counter + 1; + + if (signal_i != prev_state) begin + clk_counter <= 0; + prev_state <= signal_i; + end + + if (clk_counter == STABLE_PERIOD) begin + signal_o <= signal_i; + end end - signal_o <= signal_i; end +// Learning? +// Apparently, (and obviously, when you think about it), +// it's not possible to drive a signal by two blocks +// always @(signal_i) begin +// if (signal_i != prev_state) begin +// clk_counter <= 0; +// prev_state <= signal_i; +// end +// end + endmodule |
