(System)Verilog: Be explicit about wire/logic

1 files changed, 3 insertions, 3 deletions

diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
index bbe7a0c..fe34202 100644
--- a/eater_cpu/bus_writer.sv
+++ b/eater_cpu/bus_writer.sv
@@ -3,9 +3,9 @@
 `timescale 1us/1us
 
 module bus_writer (
-    input [7:0] in_value,
-    input in_write_to_output,
-    output [7:0] out_value
+    input wire [7:0] in_value,
+    input wire in_write_to_output,
+    output wire [7:0] out_value
 );
 
 assign out_value = in_write_to_output ? in_value : 8'bZ;