(System)Verilog: Be explicit about wire/logic

1 files changed, 6 insertions, 6 deletions

diff --git a/eater_cpu/eater_alu.sv b/eater_cpu/eater_alu.sv
index bbfb050..1474d6d 100644
--- a/eater_cpu/eater_alu.sv
+++ b/eater_cpu/eater_alu.sv
@@ -3,15 +3,15 @@
 `timescale 1us/1us
 
 module eater_alu (
-    input clk_in,
-    input en_output_in,
+    input wire clk_in,
+    input wire en_output_in,
 
-    input subtract_n_add_in,
+    input wire subtract_n_add_in,
 
-    input [7:0] A_in,
-    input [7:0] B_in,
+    input wire [7:0] A_in,
+    input wire [7:0] B_in,
 
-    output [7:0] bus_out
+    output wire [7:0] bus_out
 );
 
 wire [7:0] result = subtract_n_add_in ? (A_in - B_in) : (A_in + B_in);