(System)Verilog: Be explicit about wire/logic

1 files changed, 6 insertions, 6 deletions

diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 52c53a4..22b8f4f 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -6,16 +6,16 @@
 module eater_register #(
   parameter DATA_WIDTH = 8
 ) (
-  input clk_in,
+  input wire clk_in,
 
   // store data on rising clk?
-  input en_store_in,
+  input wire en_store_in,
   // async - output data to bus
-  input en_output_in,
+  input wire en_output_in,
 
-  input [(DATA_WIDTH-1) : 0] data_in,
-  output [(DATA_WIDTH-1) : 0] bus_out,
-  output [(DATA_WIDTH-1) : 0] always_out
+  input wire [(DATA_WIDTH-1) : 0] data_in,
+  output wire [(DATA_WIDTH-1) : 0] bus_out,
+  output wire [(DATA_WIDTH-1) : 0] always_out
   // inout [(DATA_WIDTH-1) : 0] data
   
 );