eater: Add ALU

while doing so,
add always_out port for regs

1 files changed, 12 insertions, 10 deletions

diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 17da7bd..52c53a4 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -6,30 +6,32 @@
 module eater_register #(
   parameter DATA_WIDTH = 8
 ) (
-  input clk_i,
+  input clk_in,
 
   // store data on rising clk?
-  input en_store_i,
+  input en_store_in,
   // async - output data to bus
-  input en_output_i,
+  input en_output_in,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
-  output [(DATA_WIDTH-1) : 0] data_o
+  input [(DATA_WIDTH-1) : 0] data_in,
+  output [(DATA_WIDTH-1) : 0] bus_out,
+  output [(DATA_WIDTH-1) : 0] always_out
   // inout [(DATA_WIDTH-1) : 0] data
   
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
 
-always @(posedge clk_i) begin
-  if (en_store_i) begin
-    r_datastore <= data_i;
+always @(posedge clk_in) begin
+  if (en_store_in) begin
+    r_datastore <= data_in;
     // r_datastore <= data;
   end
 end
 
-assign data_o = en_output_i ? r_datastore : 8'bz;
-// assign data = en_output_i ? r_datastore : 8'bz;
+assign bus_out = en_output_in ? r_datastore : 8'bz;
+assign always_out = r_datastore;
+// assign data = en_output_in ? r_datastore : 8'bz;
 
 endmodule