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| author | uvok | 2026-01-16 10:58:40 +0100 |
|---|---|---|
| committer | uvok | 2026-01-16 10:58:40 +0100 |
| commit | 9b15a4330d23bb9ef04f51e89a00243b75eacc8e (patch) | |
| tree | b53b1dc054b09f5003ab9d1de1aa0a5e3cf5e124 /eater_cpu/eater_register.v | |
| parent | 03e6d71e8fc98769a76e8099a1c10e8af2e43264 (diff) | |
Better tb for eater cpu
Diffstat (limited to 'eater_cpu/eater_register.v')
| -rw-r--r-- | eater_cpu/eater_register.v | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v index 6025ed1..17da7bd 100644 --- a/eater_cpu/eater_register.v +++ b/eater_cpu/eater_register.v @@ -15,6 +15,8 @@ module eater_register #( input [(DATA_WIDTH-1) : 0] data_i, output [(DATA_WIDTH-1) : 0] data_o + // inout [(DATA_WIDTH-1) : 0] data + ); reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */; @@ -22,10 +24,12 @@ reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */; always @(posedge clk_i) begin if (en_store_i) begin r_datastore <= data_i; + // r_datastore <= data; end end -assign data_o = en_output_i ? r_datastore : 'z; +assign data_o = en_output_i ? r_datastore : 8'bz; +// assign data = en_output_i ? r_datastore : 8'bz; endmodule |
