Add instruction register

1 files changed, 18 insertions, 2 deletions

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index 405d3ff..b2f9a5a 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -2,14 +2,19 @@
 
 `timescale 1us/1us
 
-module eater_computer;
+module eater_computer(
+  output [7:0] debug_bus
+);
 logic clk_in;
 
 /* verilator public_on */
 tri [7:0] bus;
 logic A_to_bus, bus_to_A,
-      B_to_bus, bus_to_B
+      B_to_bus, bus_to_B,
+      INS_to_bus, bus_to_INS
 ;
+
+assign debug_bus = bus;
 /* verilator public_off */
 
 eater_register A (
@@ -28,6 +33,17 @@ eater_register B (
   .data_o(bus)
 );
 
+tri [7:0] ins_bus_out;
+assign bus[3:0] = ins_bus_out[3:0];
+
+eater_register INS (
+  .clk_i(clk_in),
+  .en_store_i(bus_to_INS),
+  .en_output_i(INS_to_bus),
+  .data_i(bus),
+  .data_o(ins_bus_out)
+);
+
 `ifdef VERILATOR
 initial begin
   $dumpfile("simpc.vvp");