Add 1st sketch of eater cpu

2 files changed, 87 insertions, 0 deletions

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
new file mode 100644
index 0000000..405d3ff
--- /dev/null
+++ b/eater_cpu/eater_computer.sv
@@ -0,0 +1,52 @@
+// represents the Ben Eater 8bit computer
+
+`timescale 1us/1us
+
+module eater_computer;
+logic clk_in;
+
+/* verilator public_on */
+tri [7:0] bus;
+logic A_to_bus, bus_to_A,
+      B_to_bus, bus_to_B
+;
+/* verilator public_off */
+
+eater_register A (
+  .clk_i(clk_in),
+  .en_store_i(bus_to_A),
+  .en_output_i(A_to_bus),
+  .data_i(bus),
+  .data_o(bus)
+);
+
+eater_register B (
+  .clk_i(clk_in),
+  .en_store_i(bus_to_B),
+  .en_output_i(B_to_bus),
+  .data_i(bus),
+  .data_o(bus)
+);
+
+`ifdef VERILATOR
+initial begin
+  $dumpfile("simpc.vvp");
+  $dumpvars();
+
+  A_to_bus = 0;
+  B_to_bus = 0;
+  bus_to_A = 0;
+  bus_to_B = 0;
+  clk_in = 0;
+end
+
+always #2 clk_in = ~clk_in;
+
+initial begin
+
+  #10
+  $finish();
+end
+`endif
+
+endmodule
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
new file mode 100644
index 0000000..0502c8a
--- /dev/null
+++ b/eater_cpu/eater_register.v
@@ -0,0 +1,35 @@
+`timescale 1us/1us
+
+`ifndef EATER_REGISTER
+`define EATER_REGISTER
+
+module eater_register #(
+  parameter DATA_WIDTH = 8
+) (
+  input clk_i,
+
+  // sync? async?
+  input en_store_i,
+  input en_output_i,
+
+  input [(DATA_WIDTH-1) : 0] data_i,
+  output [(DATA_WIDTH-1) : 0] data_o
+);
+
+reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
+
+reg int_output_data;
+
+always @(posedge clk_i) begin
+  if (en_store_i) begin
+    r_datastore <= data_i;
+  end
+
+  int_output_data <= en_output_i;
+end
+
+assign data_o = int_output_data ? r_datastore : 'z;
+
+endmodule
+
+`endif