(System)Verilog: Be explicit about wire/logic

3 files changed, 15 insertions, 15 deletions

diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
index bbe7a0c..fe34202 100644
--- a/eater_cpu/bus_writer.sv
+++ b/eater_cpu/bus_writer.sv
@@ -3,9 +3,9 @@
 `timescale 1us/1us
 
 module bus_writer (
-    input [7:0] in_value,
-    input in_write_to_output,
-    output [7:0] out_value
+    input wire [7:0] in_value,
+    input wire in_write_to_output,
+    output wire [7:0] out_value
 );
 
 assign out_value = in_write_to_output ? in_value : 8'bZ;
diff --git a/eater_cpu/eater_alu.sv b/eater_cpu/eater_alu.sv
index bbfb050..1474d6d 100644
--- a/eater_cpu/eater_alu.sv
+++ b/eater_cpu/eater_alu.sv
@@ -3,15 +3,15 @@
 `timescale 1us/1us
 
 module eater_alu (
-    input clk_in,
-    input en_output_in,
+    input wire clk_in,
+    input wire en_output_in,
 
-    input subtract_n_add_in,
+    input wire subtract_n_add_in,
 
-    input [7:0] A_in,
-    input [7:0] B_in,
+    input wire [7:0] A_in,
+    input wire [7:0] B_in,
 
-    output [7:0] bus_out
+    output wire [7:0] bus_out
 );
 
 wire [7:0] result = subtract_n_add_in ? (A_in - B_in) : (A_in + B_in);
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 52c53a4..22b8f4f 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -6,16 +6,16 @@
 module eater_register #(
   parameter DATA_WIDTH = 8
 ) (
-  input clk_in,
+  input wire clk_in,
 
   // store data on rising clk?
-  input en_store_in,
+  input wire en_store_in,
   // async - output data to bus
-  input en_output_in,
+  input wire en_output_in,
 
-  input [(DATA_WIDTH-1) : 0] data_in,
-  output [(DATA_WIDTH-1) : 0] bus_out,
-  output [(DATA_WIDTH-1) : 0] always_out
+  input wire [(DATA_WIDTH-1) : 0] data_in,
+  output wire [(DATA_WIDTH-1) : 0] bus_out,
+  output wire [(DATA_WIDTH-1) : 0] always_out
   // inout [(DATA_WIDTH-1) : 0] data
   
 );