eater,sim: Reformat and extract func

1 files changed, 69 insertions, 61 deletions

diff --git a/eater_cpu/cpp/Veater_computer__main.cpp b/eater_cpu/cpp/Veater_computer__main.cpp
index df6b65e..8f11b21 100644
--- a/eater_cpu/cpp/Veater_computer__main.cpp
+++ b/eater_cpu/cpp/Veater_computer__main.cpp
@@ -1,10 +1,10 @@
 // Verilated -*- C++ -*-
 // DESCRIPTION: Verilator output: main() simulation loop, created with --main
 
+#include "Veater_computer.h"
 #include "Veater_computer_eater_computer.h"
 #include "Veater_computer_my_mem__DB10.h"
 #include "verilated.h"
-#include "Veater_computer.h"
 #include "verilatedos.h"
 
 #include "verilated_fst_c.h"
@@ -13,71 +13,79 @@
 
 //======================
 
-int main(int argc, char** argv, char**) {
-    // Setup context, defaults, and parse command line
-    Verilated::debug(0);
-    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
-    contextp->traceEverOn(true);
-    contextp->threads(1);
-    contextp->commandArgs(argc, argv);
-
-    // Construct the Verilated model, from Vtop.h generated from Verilating
-    const std::unique_ptr<Veater_computer> topp{new Veater_computer{contextp.get(), ""}};
-
-    // waveforms!!!
-    VerilatedFstC* tfp = new VerilatedFstC;
-    topp->trace(tfp, 100);
-    tfp->open("eater.vvp");
-
-    topp->clk_in = 0;
-    topp->auto_run_in = 1;
-
-    // init RAM
-    // LDA 14
-    topp->eater_computer->RAM->r_datastore[0] = 0x0e;
-    // ADD 15
-    topp->eater_computer->RAM->r_datastore[1] = 0x1f;
-    // OUT
-    topp->eater_computer->RAM->r_datastore[2] = 0xe0;
-    // Data @ 14
-    topp->eater_computer->RAM->r_datastore[14] = 14;
-    // Data @ 15
-    topp->eater_computer->RAM->r_datastore[15] = 28;
-    simpc_ui_init();
-
-    // Simulate until $finish
-    while (VL_LIKELY(!contextp->gotFinish()) && VL_LIKELY(contextp->time() < 100)) {
-        // Evaluate model
-        topp->eval();
-        
-        tfp->dump(contextp->time());
-        simpc_ui_write(topp, contextp->time());
-
-        // Advance time
-        contextp->timeInc(1);
-
-        topp->clk_in = !topp->clk_in;
-
-        if (topp->eater_computer->PC_out == 3 && topp->eater_computer->__PVT__decoder__DOT__internal_state == 0x01)
-            break;
-    }
-    contextp->timeInc(10);
+void load_program(const std::unique_ptr<Veater_computer> &topp) {
+  // LDA 14
+  topp->eater_computer->RAM->r_datastore[0] = 0x0e;
+  // ADD 15
+  topp->eater_computer->RAM->r_datastore[1] = 0x1f;
+  // OUT
+  topp->eater_computer->RAM->r_datastore[2] = 0xe0;
+  // Data @ 14
+  topp->eater_computer->RAM->r_datastore[14] = 14;
+  // Data @ 15
+  topp->eater_computer->RAM->r_datastore[15] = 28;
+}
+
+int main(int argc, char **argv, char **) {
+  // Setup context, defaults, and parse command line
+  Verilated::debug(0);
+  const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+  contextp->traceEverOn(true);
+  contextp->threads(1);
+  contextp->commandArgs(argc, argv);
+
+  // Construct the Verilated model, from Vtop.h generated from Verilating
+  const std::unique_ptr<Veater_computer> topp{
+      new Veater_computer{contextp.get(), ""}};
+
+  // waveforms!!!
+  VerilatedFstC *tfp = new VerilatedFstC;
+  topp->trace(tfp, 100);
+  tfp->open("eater.vvp");
+
+  topp->clk_in = 0;
+  topp->auto_run_in = 1;
+
+  // Load program
+  load_program(topp);
+
+  simpc_ui_init();
+
+  // Simulate until $finish
+  while (VL_LIKELY(!contextp->gotFinish()) &&
+         VL_LIKELY(contextp->time() < 100)) {
+    // Evaluate model
+    topp->eval();
+
     tfp->dump(contextp->time());
+    simpc_ui_write(topp, contextp->time());
+
+    // Advance time
+    contextp->timeInc(1);
+
+    topp->clk_in = !topp->clk_in;
+
+    if (topp->eater_computer->PC_out == 3 &&
+        topp->eater_computer->__PVT__decoder__DOT__internal_state == 0x01)
+      break;
+  }
+  contextp->timeInc(10);
+  tfp->dump(contextp->time());
 
-    tfp->close();
-    simpc_ui_finish_message(contextp, topp);
+  tfp->close();
+  simpc_ui_finish_message(contextp, topp);
 
-    if (VL_LIKELY(!contextp->gotFinish())) {
-        VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
-    }
+  if (VL_LIKELY(!contextp->gotFinish())) {
+    VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
+  }
 
-    // Execute 'final' processes
-    topp->final();
+  // Execute 'final' processes
+  topp->final();
 
-    // Print statistical summary report
-    contextp->statsPrintSummary();
+  // Print statistical summary report
+  contextp->statsPrintSummary();
 
-    simpc_ui_cleanup();
+  simpc_ui_cleanup();
 
-    return 0;
+  return 0;
 }