mem: Add debug for iverilog

1 files changed, 6 insertions, 0 deletions

diff --git a/my_mem.v b/my_mem.v
index e4ed4f6..6ee94ca 100644
--- a/my_mem.v
+++ b/my_mem.v
@@ -17,14 +17,20 @@ module my_mem #(
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];
+// for debugging simulations, as iverilog
+// does't show r_datastore
+reg [(DATA_WIDTH-1) : 0] r_cur_r_val;
+reg [(DATA_WIDTH-1) : 0] r_cur_w_val;
 
 always @(posedge clk_i) begin
   if (write_en_i) begin
     r_datastore[r_write_addr] <= data_i;
+    r_cur_w_val <= data_i;
   end
 
   if (read_en_i) begin
     data_o <= r_datastore[r_read_addr];
+    r_cur_r_val <= r_datastore[r_read_addr];
   end
 end