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authoruvok2026-01-01 15:58:45 +0100
committeruvok2026-01-01 15:58:45 +0100
commitea26b038d9dcf73354b4803e6e2ea91c8267c75f (patch)
tree27a41de147a88ea90bfaca0d5c90e903beed02e5 /nandgame/alu.sv
parent22ee1e65becb3ba51a97ff9e2e7e4e946ae9b928 (diff)
add ALU
Diffstat (limited to 'nandgame/alu.sv')
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1 files changed, 44 insertions, 0 deletions
diff --git a/nandgame/alu.sv b/nandgame/alu.sv
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+// nandgame ALU
+
+`timescale 1us/1us
+
+`include "nandgame_types.v"
+`include "arith_unit.sv"
+`include "logic_unit.sv"
+
+module alu #(
+ parameter DATA_WIDTH = 16
+) (
+ input [(DATA_WIDTH-1):0] X,
+ input [(DATA_WIDTH-1):0] Y,
+ input logic u,
+ input logic [1:0] opcode,
+ input logic zx,
+ input logic sw,
+
+ output logic [(DATA_WIDTH-1):0] RES
+);
+
+logic [(DATA_WIDTH-1):0] MyX = zx ? 0 : sw ? Y : X;
+logic [(DATA_WIDTH-1):0] MyY = sw ? X : Y;
+logic [(DATA_WIDTH-1):0] MyResA;
+logic [(DATA_WIDTH-1):0] MyResL;
+
+arith_unit au (
+ .X(MyX),
+ .Y(MyY),
+ .RES(MyResA),
+ .operation(opcode)
+);
+
+logic_unit lu (
+ .X(MyX),
+ .Y(MyY),
+ .RES(MyResL),
+ .operation(opcode)
+);
+
+assign RES = u ? MyResL : MyResA;
+
+
+endmodule