(System)Verilog: Be explicit about wire/logic

1 files changed, 7 insertions, 7 deletions

diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv
index b68fc22..a095f81 100644
--- a/nandgame/comb_mem.sv
+++ b/nandgame/comb_mem.sv
@@ -13,23 +13,23 @@ module comb_mem #(
   parameter DATA_WIDTH = 16
 ) (
     // store to A register
-    input store_to_a_in,
+    input wire store_to_a_in,
     // store to D register
-    input store_to_d_in,
+    input wire store_to_d_in,
     // store to address in memory pointed to by A (currently)
-    input store_to_pa_in,
+    input wire store_to_pa_in,
 
     // value to store
-    input [(DATA_WIDTH-1):0] X_in,
+    input wire [(DATA_WIDTH-1):0] X_in,
     // output registers updated on falling edge
     input wire clk_in,
 
     // content of A register
-    output reg [(DATA_WIDTH-1):0] reg_A_out,
+    output logic [(DATA_WIDTH-1):0] reg_A_out,
     // content of D register
-    output reg [(DATA_WIDTH-1):0] reg_D_out,
+    output logic [(DATA_WIDTH-1):0] reg_D_out,
     // content memory pointed to by A register
-    output reg [(DATA_WIDTH-1):0] reg_pA_out
+    output logic [(DATA_WIDTH-1):0] reg_pA_out
 );
 
 wire inv_clk_int;