Rename variables to be more clear, document

1 files changed, 28 insertions, 25 deletions

diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv
index dcda331..c7fda32 100644
--- a/nandgame/comb_mem.sv
+++ b/nandgame/comb_mem.sv
@@ -10,51 +10,54 @@ module comb_mem #(
   parameter DATA_WIDTH = 16
 ) (
     // store to A register
-    input a_i,
+    input store_to_a_in,
     // store to D register
-    input d_i,
+    input store_to_d_in,
     // store to address in memory pointed to by A (currently)
-    input pa_i,
+    input store_to_pa_in,
 
     // value to store
-    input [(DATA_WIDTH-1):0] X,
-    // nandgame updates on falling edge
-    input wire cl,
-
-    output reg [(DATA_WIDTH-1):0] A_o,
-    output reg [(DATA_WIDTH-1):0] D_o,
-    output reg [(DATA_WIDTH-1):0] pA_o
+    input [(DATA_WIDTH-1):0] X_in,
+    // output registers updated on falling edge
+    input wire clk_in,
+
+    // content of A register
+    output reg [(DATA_WIDTH-1):0] reg_A_out,
+    // content of D register
+    output reg [(DATA_WIDTH-1):0] reg_D_out,
+    // content memory pointed to by A register
+    output reg [(DATA_WIDTH-1):0] reg_pA_out
 );
 
-wire inv_clk;
+wire inv_clk_int;
 // my hw uses posedge, nandgame uses negedge.
-assign inv_clk = ~cl;
+assign inv_clk_int = ~clk_in;
 
 my_mem #(
     .DATA_WIDTH(DATA_WIDTH),
     // limit memory
     .DATA_DEPTH(1024)
 ) nand_memory (
-    .clk_i(inv_clk),
-    .write_en_i(pa_i),
+    .clk_i(inv_clk_int),
+    .write_en_i(store_to_pa_in),
     .read_en_i(1'b1),
-    .r_read_addr(A_o),
-    .r_write_addr(A_o),
-    .data_o(pA_o),
-    .data_i(X)
+    .r_read_addr(reg_A_out),
+    .r_write_addr(reg_A_out),
+    .data_o(reg_pA_out),
+    .data_i(X_in)
 );
 
 initial begin
-    A_o = 0;
-    D_o = 0;
+    reg_A_out = 0;
+    reg_D_out = 0;
 end
 
-always @(negedge cl) begin
-    if (a_i)
-        A_o <= X;
+always @(negedge clk_in) begin
+    if (store_to_a_in)
+        reg_A_out <= X_in;
 
-    if (d_i)
-        D_o <= X;
+    if (store_to_d_in)
+        reg_D_out <= X_in;
 end
 
 endmodule