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authoruvok2026-01-01 18:34:01 +0100
committeruvok2026-01-01 18:34:01 +0100
commitee40665fa366b2153e9e3826a65f62cb48bd413f (patch)
tree3d9dc9bbd9e46c8a4f906af057c5483ebd6bce7e /nandgame/comb_mem.sv
parent54af62ca18ef8fabdd359dc6e855e33241dd4788 (diff)
try to implement comb_mem
Diffstat (limited to 'nandgame/comb_mem.sv')
-rw-r--r--nandgame/comb_mem.sv56
1 files changed, 56 insertions, 0 deletions
diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv
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+`timescale 1us/1us
+
+`include "../my_mem.v"
+
+module comb_mem #(
+ parameter DATA_WIDTH = 16
+) (
+ // store to A register
+ input a_i,
+ // store to D register
+ input d_i,
+ // store to address in memory pointed to by A (currently)
+ input pa_i,
+
+ // value to store
+ input [(DATA_WIDTH-1):0] X,
+ // nandgame updates on falling edge
+ input wire cl,
+
+ output reg [(DATA_WIDTH-1):0] A_o,
+ output reg [(DATA_WIDTH-1):0] D_o,
+ output reg [(DATA_WIDTH-1):0] pA_o
+);
+
+wire inv_clk;
+// my hw uses posedge, nandgame uses negedge.
+assign inv_clk = ~cl;
+
+my_mem #(
+ .DATA_WIDTH(DATA_WIDTH),
+ // limit memory
+ .DATA_DEPTH(1024)
+) nand_memory (
+ .clk_i(inv_clk),
+ .write_en_i(pa_i),
+ .read_en_i(1'b1),
+ .r_read_addr(A_o),
+ .r_write_addr(A_o),
+ .data_o(pA_o),
+ .data_i(X)
+);
+
+initial begin
+ A_o = 0;
+ D_o = 0;
+end
+
+always @(negedge cl) begin
+ if (a_i)
+ A_o <= X;
+
+ if (d_i)
+ D_o <= X;
+end
+
+endmodule