(System)Verilog: Be explicit about wire/logic

1 files changed, 8 insertions, 8 deletions

diff --git a/nandgame/hack_alu.sv b/nandgame/hack_alu.sv
index 93d7476..94e30b9 100644
--- a/nandgame/hack_alu.sv
+++ b/nandgame/hack_alu.sv
@@ -10,24 +10,24 @@ module  alu #(
   parameter DATA_WIDTH = 16
 ) (
   // "X" operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // "Y" operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
 
   // zero X
-  input zx,
+  input wire zx,
   // negate X
-  input nx,
+  input wire nx,
   // zero Y
-  input zy,
+  input wire zy,
   // negate Y
-  input ny,
+  input wire ny,
 
   // "u" flag. 1=add, 0=and
-  input logic f_arith_nlogic_in,
+  input wire f_arith_nlogic_in,
 
   // negate output
-  input logic neg_out,
+  input wire neg_out,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out,