(System)Verilog: Be explicit about wire/logic

1 files changed, 10 insertions, 10 deletions

diff --git a/nandgame/instruction_decode.sv b/nandgame/instruction_decode.sv
index b78bee8..4cd7e97 100644
--- a/nandgame/instruction_decode.sv
+++ b/nandgame/instruction_decode.sv
@@ -15,28 +15,28 @@ module instruction_decode  #(
   parameter DATA_WIDTH = 16
 ) (
   // instruction to decode
-  input [15:0] instruction_in,
+  input wire [15:0] instruction_in,
   
   // value of A register
-  input [(DATA_WIDTH-1):0] A_in,
+  input wire [(DATA_WIDTH-1):0] A_in,
   // value of D register
-  input [(DATA_WIDTH-1):0] D_in,
+  input wire [(DATA_WIDTH-1):0] D_in,
   // content of memory at address in A register
-  input [(DATA_WIDTH-1):0] pA_in,
+  input wire [(DATA_WIDTH-1):0] pA_in,
   
   // result of operation
-  output [(DATA_WIDTH-1):0] result_out,
+  output wire [(DATA_WIDTH-1):0] result_out,
   // whether a jump should occur
-  output do_jump_out,
+  output wire do_jump_out,
 
   // whether result should be stored to A
-  output dst_A_out,
+  output wire dst_A_out,
   // whether result should be stored to D
-  output dst_D_out,
+  output wire dst_D_out,
   // whether result should be stored in memory at address in A register
-  output dst_pA_out,
+  output wire dst_pA_out,
   // Invalid instruction
-  output invalid_ins
+  output wire invalid_ins
 );
 
 wire is_immediate_int;