(System)Verilog: Be explicit about wire/logic

1 files changed, 3 insertions, 3 deletions

diff --git a/nandgame/logic_unit.sv b/nandgame/logic_unit.sv
index 68f5c23..9207806 100644
--- a/nandgame/logic_unit.sv
+++ b/nandgame/logic_unit.sv
@@ -11,11 +11,11 @@ module logic_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see LogicCode
-  input LogicCode logic_operation_in,
+  input wire LogicCode logic_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out