fix cunter, add testbench

2 files changed, 65 insertions, 1 deletions

diff --git a/nandgame/counter.sv b/nandgame/counter.sv
index 8fa1d2b..78f054e 100644
--- a/nandgame/counter.sv
+++ b/nandgame/counter.sv
@@ -12,7 +12,7 @@ module  counter #(
   // and "outputs" on falling clock,
   // use "regular" stuff??? 
   input wire cl,
-  output reg [(DATA_WIDTH-1):0] RES
+  output wire [(DATA_WIDTH-1):0] count
 );
 
 
@@ -32,4 +32,19 @@ st	cl
 output is the current output of the component. next becomes the current output when cl changes to 0.
 */
 
+reg [(DATA_WIDTH-1):0] r_ctr;
+
+initial begin
+  r_ctr = 0;
+end
+
+always @(negedge cl) begin
+  if (st)
+    r_ctr <= X;
+  else
+    r_ctr <= r_ctr + 1;
+end
+
+assign count = r_ctr;
+
 endmodule
diff --git a/nandgame/counter_tb.sv b/nandgame/counter_tb.sv
new file mode 100644
index 0000000..a7fab85
--- /dev/null
+++ b/nandgame/counter_tb.sv
@@ -0,0 +1,49 @@
+`timescale 1us/1us
+
+module counter_tb;
+
+logic clk_i, store;
+logic [15:0] in, res;
+
+counter uut (
+  .cl(clk_i),
+  .X(in),
+  .count(res),
+  .st(store)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="counter.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  store = 0;
+  in = 0;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #200
+  @(posedge clk_i);
+  store = 1;
+  in = 16'd834;
+  repeat(3) begin
+    @(posedge clk_i);
+    assert (res == 834)
+    else   $error("Expected 834, got %d", res);
+  end
+  store = 0;
+  @(posedge clk_i);
+  assert (res == 835)
+  else   $error("Expected 835, got %d", res);
+  #30
+
+  $finish();
+end
+
+endmodule