(System)Verilog: Be explicit about wire/logic

9 files changed, 41 insertions, 41 deletions

diff --git a/nandgame/alu.sv b/nandgame/alu.sv
index 54297c9..5f82a64 100644
--- a/nandgame/alu.sv
+++ b/nandgame/alu.sv
@@ -13,17 +13,17 @@ module  alu #(
   parameter DATA_WIDTH = 16
 ) (
   // "X" operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // "Y" operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // "u" flag. 1=arithmetic, 0=logic operation
-  input logic u_arith_nlogic_in,
+  input wire u_arith_nlogic_in,
   // opcode, see ArithCode / LogicCode
-  input logic [1:0] opcode_in,
+  input wire [1:0] opcode_in,
   // zero the "X" operand
-  input logic zx_in,
+  input wire zx_in,
   // swap "X" and "Y" operands
-  input logic sw_in,
+  input wire sw_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
diff --git a/nandgame/arith_unit.sv b/nandgame/arith_unit.sv
index 53ea17e..75736ab 100644
--- a/nandgame/arith_unit.sv
+++ b/nandgame/arith_unit.sv
@@ -11,11 +11,11 @@ module  arith_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see ArithCode
-  input ArithCode arith_operation_in,
+  input wire ArithCode arith_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv
index b68fc22..a095f81 100644
--- a/nandgame/comb_mem.sv
+++ b/nandgame/comb_mem.sv
@@ -13,23 +13,23 @@ module comb_mem #(
   parameter DATA_WIDTH = 16
 ) (
     // store to A register
-    input store_to_a_in,
+    input wire store_to_a_in,
     // store to D register
-    input store_to_d_in,
+    input wire store_to_d_in,
     // store to address in memory pointed to by A (currently)
-    input store_to_pa_in,
+    input wire store_to_pa_in,
 
     // value to store
-    input [(DATA_WIDTH-1):0] X_in,
+    input wire [(DATA_WIDTH-1):0] X_in,
     // output registers updated on falling edge
     input wire clk_in,
 
     // content of A register
-    output reg [(DATA_WIDTH-1):0] reg_A_out,
+    output logic [(DATA_WIDTH-1):0] reg_A_out,
     // content of D register
-    output reg [(DATA_WIDTH-1):0] reg_D_out,
+    output logic [(DATA_WIDTH-1):0] reg_D_out,
     // content memory pointed to by A register
-    output reg [(DATA_WIDTH-1):0] reg_pA_out
+    output logic [(DATA_WIDTH-1):0] reg_pA_out
 );
 
 wire inv_clk_int;
diff --git a/nandgame/computer.sv b/nandgame/computer.sv
index 5c2127f..3286bfe 100644
--- a/nandgame/computer.sv
+++ b/nandgame/computer.sv
@@ -8,8 +8,8 @@
 `include "counter.sv"
 
 module computer (
-  input clk_in,
-  output halt
+  input wire clk_in,
+  output wire halt
 );
 
 wire nclk_int;
diff --git a/nandgame/cond_check.sv b/nandgame/cond_check.sv
index 3961313..6aa8289 100644
--- a/nandgame/cond_check.sv
+++ b/nandgame/cond_check.sv
@@ -9,7 +9,7 @@ module  cond_check #(
   parameter DATA_WIDTH = 16
 ) (
   // operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // check whether operand < 0
   input wire check_ltz_in,
   // check whether operand == 0
diff --git a/nandgame/counter.sv b/nandgame/counter.sv
index 90afa9b..2089194 100644
--- a/nandgame/counter.sv
+++ b/nandgame/counter.sv
@@ -9,7 +9,7 @@ module  counter #(
   parameter DATA_WIDTH = 16
 ) (
   // input / value to store in counter
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // whether to store input (else increment)
   input wire st_store_X_in,
   // clock
diff --git a/nandgame/hack_alu.sv b/nandgame/hack_alu.sv
index 93d7476..94e30b9 100644
--- a/nandgame/hack_alu.sv
+++ b/nandgame/hack_alu.sv
@@ -10,24 +10,24 @@ module  alu #(
   parameter DATA_WIDTH = 16
 ) (
   // "X" operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // "Y" operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
 
   // zero X
-  input zx,
+  input wire zx,
   // negate X
-  input nx,
+  input wire nx,
   // zero Y
-  input zy,
+  input wire zy,
   // negate Y
-  input ny,
+  input wire ny,
 
   // "u" flag. 1=add, 0=and
-  input logic f_arith_nlogic_in,
+  input wire f_arith_nlogic_in,
 
   // negate output
-  input logic neg_out,
+  input wire neg_out,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out,
diff --git a/nandgame/instruction_decode.sv b/nandgame/instruction_decode.sv
index b78bee8..4cd7e97 100644
--- a/nandgame/instruction_decode.sv
+++ b/nandgame/instruction_decode.sv
@@ -15,28 +15,28 @@ module instruction_decode  #(
   parameter DATA_WIDTH = 16
 ) (
   // instruction to decode
-  input [15:0] instruction_in,
+  input wire [15:0] instruction_in,
   
   // value of A register
-  input [(DATA_WIDTH-1):0] A_in,
+  input wire [(DATA_WIDTH-1):0] A_in,
   // value of D register
-  input [(DATA_WIDTH-1):0] D_in,
+  input wire [(DATA_WIDTH-1):0] D_in,
   // content of memory at address in A register
-  input [(DATA_WIDTH-1):0] pA_in,
+  input wire [(DATA_WIDTH-1):0] pA_in,
   
   // result of operation
-  output [(DATA_WIDTH-1):0] result_out,
+  output wire [(DATA_WIDTH-1):0] result_out,
   // whether a jump should occur
-  output do_jump_out,
+  output wire do_jump_out,
 
   // whether result should be stored to A
-  output dst_A_out,
+  output wire dst_A_out,
   // whether result should be stored to D
-  output dst_D_out,
+  output wire dst_D_out,
   // whether result should be stored in memory at address in A register
-  output dst_pA_out,
+  output wire dst_pA_out,
   // Invalid instruction
-  output invalid_ins
+  output wire invalid_ins
 );
 
 wire is_immediate_int;
diff --git a/nandgame/logic_unit.sv b/nandgame/logic_unit.sv
index 68f5c23..9207806 100644
--- a/nandgame/logic_unit.sv
+++ b/nandgame/logic_unit.sv
@@ -11,11 +11,11 @@ module logic_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see LogicCode
-  input LogicCode logic_operation_in,
+  input wire LogicCode logic_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out