Implement halting

2 files changed, 17 insertions, 3 deletions

diff --git a/nandgame/computer.sv b/nandgame/computer.sv
index b706d7f..7f42c05 100644
--- a/nandgame/computer.sv
+++ b/nandgame/computer.sv
@@ -8,7 +8,8 @@
 `include "counter.sv"
 
 module computer (
-  input clk_in
+  input clk_in,
+  output halt
 );
 
 wire nclk_int;
@@ -68,7 +69,9 @@ instruction_decode CPU (
   .D_in(reg_D_int),
   .pA_in(reg_pA_int),
 
-  .result_out(result_int)
+  .result_out(result_int),
+
+  .invalid_ins(halt)
 );
 
 counter PC (
@@ -78,4 +81,10 @@ counter PC (
   .st_store_X_in(cpu_do_jump_int)
 );
 
+`ifdef VERILATE
+initial begin
+  $dumpfile("simpc.vvp"); $dumpvars();
+end
+`endif
+
 endmodule
diff --git a/nandgame/instruction_decode.sv b/nandgame/instruction_decode.sv
index f81f251..b78bee8 100644
--- a/nandgame/instruction_decode.sv
+++ b/nandgame/instruction_decode.sv
@@ -34,7 +34,9 @@ module instruction_decode  #(
   // whether result should be stored to D
   output dst_D_out,
   // whether result should be stored in memory at address in A register
-  output dst_pA_out
+  output dst_pA_out,
+  // Invalid instruction
+  output invalid_ins
 );
 
 wire is_immediate_int;
@@ -42,6 +44,9 @@ wire is_immediate_int;
 // bit 15 unset = immediate
 assign is_immediate_int = !instruction_in[15];
 
+// bit 14 must be 1
+assign invalid_ins = instruction_in[15] == 1 && instruction_in[14] == 0;
+
 assign dst_A_out = is_immediate_int || instruction_in[5];
 assign dst_D_out = !is_immediate_int && instruction_in[4];
 assign dst_pA_out = !is_immediate_int && instruction_in[3];